CS302 - Digital Logic Design Assignment No. 4 Solution Fall 2016 Due Date Feb 09, 2017 

Assignment No. 04
Semester: Fall  2016
Digital Logic Design – CS302

Lectures:29-37

 

Total Marks: 20

 

Due Date: 09-Feb, 2017

 

Objectives:

Learn about state machines

Instructions:

Please read the following instructions carefully before submitting assignment:

It should be clear that your assignment will not get any credit if:

 

  • The assignment is submitted after due date.
  • The assignment is submitted via email.
  • The assignment is copied from Internet or from any other student.
  • The submitted assignment does not open or file is corrupt.
  • It is in some format other than .doc/docx.

 

Note: All types of plagiarism are strictly prohibited.

 

For any query about the assignment, contact at CS302@vu.edu.pk

 

 

Important!

You have to provide all the steps of processing in all questions otherwise, marks will be deducted. Pictures of hand written/drawn diagram will also be marked as ZERO.

Question No. 01                                                                                                                         Marks 15

A Mealy machine is a finite state machine whose output values are determined both by its current state and its current input. The next state is determined by considering input and noting the subsequent output accordingly.

0/0

 

Given the state diagram below generate the state table and design a sequential circuit using D flip flops.

 

 

 

 


                                                                                                        

 

 

 

 

Question No. 02                                                                                                                         Marks 5

Derive the  state diagram of the 3 bit sequential circuit having X as input with the following conditions in mind:

  • When X=0, it counts one by one.
  • When X=1, it counts two by two.

 

 

BEST OF LUCK

 

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